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Unit 2 |
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CISC and RISC Processors [RGPV JUN 15(7)] The popular examples of Complex Instruction Set
Computing (CISC) processors are Intel 80486, the Motorola 68040, the VAX/8600, and the IBM
S/390. CISC architecture typically use microprogrammed control units, have
lower clock rates, and higher CPI and are located at the upper left of design
space. Reduced Instruction Set Computing (RISC) processors
like the Intel i860, SPARC, MIPS R3000, and IBM RS/6000 have hard-wired
control units, higher clock rates, and lower CPI approximately one to two cycles and are located below
CISC processors in designspace. Designed to issue one instruction per cycle
RISC and CISC scalar processors should have same performance if clock rate and
program lengths are equal. RISC moves less frequent operations into software, thus
dedicating hardware resources to the most frequently used operations. RISC Scalar Processors: A special subclass of RSIC processors are the superscalar processors which allow multiple instruction to be issued
simultaneously during the cycle Instruction Set Architectures Computers are classified on the basis on instruction set they have CISC Many different instructions Many different operand data types Many different operand addressing formats Relatively small number of general purpose
registers Many instructions directly match high-level language constructions RISC Many fewer instructions than CISC (freeing chip space for more
functional units!) Fixed instruction format (e.g. 32 bits) and simple operand
addressing Relatively large number of registers Small CPI (close to 1) and high clock rates Architectural
Distinctions CISC Unified cache for instructions and data (in most cases) Microprogrammed control units and ROM in earlier processors
(hard-wired controls units now in some CISC systems) RISC Separate instruction and data caches Hard-wired control units RISC Scalar Processors Designed to issue one instruction per cycle RISC and CISC scalar
processors should have same performance if clock rate and program lengths are
equal. RISC moves less frequent operations into software, thus dedicating
hardware resources to the most frequently used operations. Representative systems: Sun SPARC, Intel i860, Motorola M88100, AMD
29000 CISC Advantages
RISC Advantages
RISC Problems
SPARCs and Register Windows The SPARC architecture makes clever use of the logical procedure
concept. Each procedure usually has some input parameters, some local
variables, and some arguments it uses to call still other procedures. The SPARC registers are arranged so that the registers addressed as
Outs in one procedure become available as Ins in a called procedure, thus
obviating the need to copy data between registers. This is similar to the concept of a
stack frame in a higher level language.
Reference{ Advance computer architecture ,Kai Hwang}
UNIT-2 Superscalar Processors [ RGPV JUN
13(10),JUN 15(2)] Scalar processor: executes one instruction per
cycle, with only one instruction pipeline. Superscalar processor: multiple instruction
pipelines, with multiple instructions issued per cycle, and multiple results generated per cycle.
This subclass of the RISC processors that allows
multiple instructions to be issued simultaneously during each cycle. The
effective CPI of a superscalar processor should be less than that of a generic scalar RISC processor.
Clock rates of scalar RISC and Superscalar RISC machines are similar. A typical superscalar will have multiple instruction pipelines an
instruction cache that can provide multiple instructions per fetch multiple buses among the
function units. In theory, all functional units can be simultaneously active.
Superscalar Constraints It should be obvious that two instructions may not be issued at the
same time (e.g. in a superscalar processor) if they are not independent. This restriction
ties the instruction-level parallelism directly to the code being executed The instruction-issue degree in a superscalar processor is
usually limited to 2 to 5 in practice. Superscalar Pipelines One or more of the pipelines in a superscalar
processor may stall if insufficient functional units exist to perform an instruction phase (fetch,
decode, execute, write back). Ideally, no more than one stall cycle should
occur. In theory, a superscalar processor should be ab le to achieve the same effective parallelism
as a vector machine with
equivalent functional units. A typical superscalar will have multiple instruction pipelines an
instruction cache that can provide multiple instructions per fetch multiple buses among the
function units In theory, all functional units can be simultaneously active. VLIW Machines Very Long Instruction Word machines typically have many more
functional units that superscalars (and thus the need for longer 256 to
1024 bits instructions to provide control for them). These machines mostly
use microprogrammed control units with relatively slow clock rates because of
the need to use ROM to hold the microcode. VLIW Architecture VLIW = Very Long Instruction Word Instructions
usually hundreds of bits long. Each instruction word essentially carries
multiple short instructions. Each of the short instructions are effectively issued at the same time. (This is
related to the long words frequently used in microcode.) Compilers for VLIW
architectures should optimally try to predict branch outcomes to properly group
instructions. VLIW Opportunities Random parallelism among scalar operations is
exploited in VLIW, instead of regular parallelism in a vector or SIMD machine. The
efficiency of the machine is entirely dictated by the success, or goodness,
of the compiler in planning the operations to be placed in the same
instruction words. Different implementations of the same VLIW architecture
may not be binary-compatible with each other, resulting in different
latencies. Pipelining in VLIW
Processors
VLIW Advantages
Reference{ Advance computer architecture ,Kai Hwang} UNIT 2
Hierarchical Memory Technology [ RGPV JUN 15(3),JUN 14(7)] As we now variety of memories are available in
market. These memories are categorized according to their properties like
speed of accessing the data, capacity to storage of data, whether it is
volatile or non volatile nature, how data are stored and how it is accessed,
rate with data are transferred etc. As an end user the most important points
that one consider while designing the memory
organization for a computer are: Its size (capacity), speed (access time),
cost and how frequently it will be accessed by the processor. If we want the increase the speed of the system the
major concern it to improve the performance of the two important and most
used components of the system that are processor and memory. If the relative
speed of processors and memories are considered, it is observed technology
present today are so that the processors speed increase by a factor of about
10000 if the speed of memory is doubled. Hence even if the speed of processor
is increased the overall speed of system will not increase in same ratio
because of bottle neck created by memory. The main choice of memory designers
is establish a balance between speed and capacity. The common used devices for storage are registers,
RAM, ROM, Hard disk, Magnetic tape, CD ROM etc. Among these fastest
memory units are registers having access times below 10ns but has the lowest capacity of few KB of
words while the slow devices are like magnetic disk and magnetic tape can
storage large amount of data i.e., have high capacity of few GBytes but same
time access times of several seconds. Thus to implement a balance between
speed and capacity we should employ a memory hierarchy in a system such that
high speed memories, which are expensive and faster and comparatively smaller
size should hold preferably the most recently accessed items kept that need
to be close to the CPU and successively large and slow memories are kept away
from the CPU to hold complete back up of data. This way of designing a memory
system is called a memory hierarchy .Memory in system is usually
characterized as appearing at various levels (0, 1,
) in a hierarchy, with
level 0 being CPU registers and level 1 being the cache closest to the CPU.
Each level is characterized by following parameters: access time ti (round-trip time from CPU to ith level) memory size si (number of bytes or words in the level) cost per byte ci transfer bandwidth bi (rate of transfer between levels) unit of transfer xi (grain size for transfers) As one goes down the hierarchy the following occur: Decrease in cost per bit Increase in capacity Increase in access time Decrease in frequency of access of the memory by the processor Principle of Locality : It is very common trend of Programs to reuse data
and instructions that are used recently. Based on this observation comes
important program property called locality of references: the instructions
and data in a program that will be used in the near future is based
on its accesses in the recent past. There is a famous 40/10 rule that comes
from empirical observation is: "A program spends 40% of its time in 10% of its code" These localities can be categorized of three types: a. Temporal locality: states that data items and code that are recently accessed are
likely to be accessed in the near future. Thus if
location M is referenced at time t, then it (location M) will be referenced
again at some time t+Dt. b. Spatial locality: states that items try to reside in proximity in the memory i.e., the
items whose addresses are near to each other are likely to be referred
together in time. Thus we can say memory accesses
are clustered with respect to the address space. Thus
if location M is referenced at time t, then another location M±Dm will be
referenced at time t+Dt. c. Sequential locality: Programs are stored sequentially in memory and normally these programs
has sequential trend of execution. Thus we say
instructions are stored in memory in certain array patterns and are accessed
sequentially one memory locations after another. Thus
if location M is referenced at time t, then locations M+1, M+2,
will be
referenced at time t+Dt, t+Dt, etc. In each of these patterns, both Dm and
Dt are small. H&P suggest that 90 percent of the execution
time in most programs is spent executing only 10 percent of the code. One of
the implications of the locality is data and instructions should have
separate data and instruction caches. The main advantage of separate caches
is that one can fetch instructions and operands simultaneously. This concept
is basis of the design known as Harvard architecture, after the Harvard Mark
series of electromechanical machines, in which the instructions were supplied
by a separate unit. Inclusion property : If a value is found at one level, it should be
present at all of the levels below it. M1 C M2 C M3------ The implication of the inclusion property is that
all items of information in the innermost memory level (cache) also appear
in the outer memory levels.The inverse, however, is
not necessarily true. That is, the presence of a data item in level Mi+1 does not imply its presence in level
Mi. We call a reference to a missing item a miss. The Coherence
Property The value of any data should be consistent at all
level. The inclusion property is, of course, never completely true, but it
does represent a desired state. That is, as information is modified by the
processor, copies of that information should be placed in the appropriate
locations in outer memory levels. The requirement that copies of data items
at successive memory levels be consistent is called the coherence property.
Reference{ Advance computer architecture ,Kai Hwang} UNIT-2
Memory capacity Planning [RGPV JUN 13(10)] As any program use mainly some portion of it at a
given time i.e., the programs access a restricted portion of their address
space in any time. So the portion that program may
need should kept at higher level and remaining program at lower level.
Locality is entirely program-dependent. Most caches implement locality
assuming sequential code. In most programs, memory references are assumed to
occur in patterns that are strongly related (statistically) to each as
discussed in reference of locality. Working Sets The set of addresses (bytes, pages, etc.) referenced
by a program during the interval from t to t+w, where w is called the working
set parameter, changes slowly. This set of addresses, called the working set,
should be present in the higher levels of M if a program is to execute
efficiently (that is, without requiring numerous movements of data items from
lower levels of M). This is called the working set principle. Hit Ratios When a needed item (instruction or data) is found in
the level of the memory hierarchy being examined, it is called a hit.
Otherwise (when it is not found), it is called a miss (and the item must be
obtained from a lower level in the hierarchy). The hit ratio, h, for Mi is the probability (between
0 and 1) that a needed data item is found when sought in level memory Mi. The
miss ratio is obviously just 1-hi. We assume h0 = 0 and hn = 1. To evaluate the effectiveness of the memory hierarchy the following
formula is used: Memory_stall_cycles = IC * Mem_Refs * Miss_Rate * Miss_Penalty Where IC = Instruction count Mem_Refs = Memory References per Instruction Miss_Rate = the fraction of accesses that are not in the given memory Miss_Penalty = the additional time to service the miss The hit ratio is an important measure of the
performance of a memory level and is the probability that a reference is to a
value already in a given level of the hierarchy. The miss ratio is 1 - h. Thus if any data is not present in given level of memory
it should go to lower hierarchy level. The Miss penalty time is the sum of
the access frequencies times their corresponding access times where the
access frequency is the product of the hit ratio for the given level with the
miss ratios of all higher levels Memory Generalities It is almost always the case that memories at
lower-numbered levels, when compare to those at higher-numbered levels are
faster to access, are smaller in capacity, are more expensive per byte, have
a higher bandwidth, and have a smaller unit of transfer. In general, then, ti-1 < ti, si-1 < si, ci-1
> ci, bi-1 > bi, and xi-1 < xi. Access Frequencies The access frequency fi to level Mi is (1-h1) * (1-h2)*
* hi. Note that f1 = h1 and Effective Access Times There are different penalties associated with misses
at different levels in the memory hierarchy. A cache miss is typically 2 to 4
times as expensive as a cache hit (assuming success at the next level). A page fault (miss) is 3 to 4 magnitudes as costly
as a page hit. The effective access time of a memory hierarchy can be
expressed as The first few terms in this expression dominate, but
the effective access time is still dependent on program behavior and memory
design choices. Hierarchy Optimization Given most, but not all, of the various parameters
for the levels in a memory hierarchy, and some desired goal (cost,
performance, etc.), it should be obvious how to proceed in determining the
remaining parameters.
UNIT 2
Introduction; [
RGPV JUN 15(2),JUN 13(10)] With large memories, many
memory chips must be assembled together to make one memory system. One issue
to be addressed in interleaving.
Interleaving is the process of organizing something. Memory
interleaving is the process of organizing of memory spaces. Example: A memory of
Interleaving
is the process of organizing something. Memory interleaving is the process of
organizing of memory spaces. There are
two types of memory interleaving 1. High
Order memory interleaving 2. Low
Order memory interleaving To speed up the memory
operations (read and write), the main memory of In general, the CPU is more likely to need to access the memory for a
set of consecutive words (either a segment of consecutive instructions in a
program or the components of a data structure such as an array, the
interleaved (low-order) arrangement is preferable as consecutive words are in
different modules and can be fetched simultaneously. In case of high-order
arrangement, the consecutive words are usually in one module, having multiple
modules is not helpful if consecutive words are needed. Some Applications It is important to keep some actual applications in mind, such as: Gaussian elimination. Recall that a typical operation is to add a
multiple of one row of our matrix to another row of the matrix. Matrix multiplication. Recall that to do AB = C for matrices A, B
and C, we get Cij by taking the inner product (dot product) of As ith row
and Bs jth column. Image processing, such as in Adobe Photoshop or the open-source
GIMP. Here element (i,j) element in our matrix would
be the brightness at the pixel (i,j). If we wish our image to look smoother,
then at each pixel we would average the brightness at neighboring points, and
make this value average our new brightness at the given point. Role of interleaving in Shared
memory multiprocessor High-order interleaving is useful in shared-memory
multiprocessor systems. Here the goal is to minimize the number of times two
or more processors need to use the same module at the same time, a situation
which causes delay while processors wait for each other. If the system is
configured for high-order interleaving, application software in a way to
minimize such conflicts. In matrix
applications, for instance, we can partition the matrix into blocks, and have
different processors work on different blocks. In image processing
applications, we can have different processors work on different parts of the
image. Such partitioning almost never works perfectlye.g. computation for
one part of an image may need information from another partbut if we are careful we can get good results.
UNIT 2
Backplane Buses [RGPV JUN 12(10)] A backplane bus interconnects
processors, data storage and peripheral devices in a tightly coupled
hardware. The system bus must be designed to allow communication between
devices on the devices on the bus without disturbing the internal activities
of all the devices attached to the bus. These are typically `intermediate'
buses, used to connect a variety of other buses to the CPU-Memory bus. They
are called Backplane Buses because they are restricted to the backplane of
the system. Backplane bus specification They are generally connected to the CPU-Memory bus
by a bus adaptor, which handles translation between the buses.
Commonly, this is integrated into the CPU-Memory bus controller logic. While
these buses can be used to directly control devices, they are used as
'bridges` to other buses. For example, AGP bus devices i.e. video
cards act as bridges between the CPU-Memory bus and the actual display
device: the monitor(s).) For this reason, these buses are sometimes called mezzanine
buses. Allow processors, memory and I/O devices to coexist on single bus Balance demands of processor-memory communication with demands of
I/O device-memory communication Interconnects the circuit boards containing processor, memory and
I/O interfaces an interconnection structure within the chassis Cost advantage: one single bus for all components The backplane bus is divided into four groups Data address and control lines form the data transfer bus (DTB) in
VME bus. DTB Arbitration bus that provide control of DTB to requester using
the arbitration logic. Interrupt and Synchronization bus used for handling interrupt Utility bus include signals that provide periodic timing and
coordinate the power up and power down sequence of the system The backplane bus is made of signal lines and
connectors. A special bus controller board is used to house the backplane
control logic, such as the system clock driver, arbiter, bus timer and power
driver. Functional module : A
functional module is collection of electronic circuitry that reside on one
functional board and works to achieve special bus control function. These
functions are: A arbitrator is a functional module that accepts bus request from the
requester module and grant control of the DTB to one request at a time. A bus timer measures the time each data transfer
takes on the DTB and terminates the DTB cycle if a transfer take too long. An interrupter module generates an interrupt request
and provide status /ID information when an interrupt handler module request
it. A location monitor is a functional module that
monitors data transfer over the DTB. A power monitor watches the status of the power
source and signals when power unstable. A system clock driver is a module that provides a
clock timing signal on the utility bus. In addition, board interface logic is
needed to match the signal line impedence, the propagation time and
termination values between the backplane and the plug in
board.
UNIT 2
Addressing and Timing Protocols [RGPV JUN 14,15(7)]
Two types of printed circuit boards
connected to a bus: active and passive
The master can initiate a bus cycle
Only one can be in control at a
time
The slaves respond to requests by a
master
Multiple slaves can respond. Bus Addressing
The backplane bus is driven by a
digital clock with a fixed cycle time: bus cycle
Backplane has limited physical
size, so will not skew information
Factors affecting bus delay:
Sources line drivers,
destinations receivers, slot capacitance, line length, and bus loading
effects
Design should minimize overhead
time, so most bus cycles used for useful operations
Identify each board with a slot
number
When slot # matches contents of
high-order address lines, the board is selected as a slave (slot addressing)
Broadcall and Broadcast
Most bus transactions have one
slave/master
Broadcall: read operation where
multiple slaves place data on bus
detects multiple interrupt sources
Broadcast: write operation
involving multiple slaves
Implements multicache coherence on
the bus Synchronizing Timing Protocol Synchronous timing
All bus transaction steps take
place at fixed clock edges
Clock cycle time determined by
slowest device on bus
Data-ready pulse (master) initiates
transfer
Data-accept (slave) signals
completion
Simple, less circuitry, for similar
device speeds Asynchronous timing
Based on handshaking or
interlocking
Provides freedom of variable length
clock signals for different speed devices
No fixed clock cycle
No response time restrictions
More complex and costly, but more
flexible
UNIT 2 Arbitration
Process of selecting next bus master
Bus tenure is duration of control
Arbitrate on a fairness or priority basis
Arbitration competition and bus transactions take place
concurrently on a parallel bus over separate lines Transaction mode
Connected: carry out masters request and a slaves response in a
single bus transaction
Split: splits request and response into separate transaction Arbitration It is the process
of selecting the next master to gain access of the bus. There are three
arbitration schemes
Potential masters
are daisy chained
Signal line propagates bus-grant from first master
to the last master
Only one bus-request line
The bus-grant line activates the bus-busy line Advantages;
Simple scheme
Easy to add devices
Fixed-priority sequence not fair
Propagation of bus-grant signal is
slow
Not fault tolerant
·
Provide independent bus-request and
grant signals for each master ·
Require a central arbiter, but can
use a priority or fairness based policy ·
More flexible and faster than a
daisy-chained policy Larger number of lines costly
Each master has its own arbiter and unique
arbitration number
Use arbitration # to resolve
competition
Send # to SBRG lines and compare
own # with SBRG #Priority based scheme Transaction Modes
Connected: carry out masters request and a slaves response
in a single bus transaction
Split: splits request and response into separate transactions
Allow devices with long latency or
access time to use bus resources more efficiently
May require two or more connected
bus transactions Interrupt Mechanisms
Interrupt: request from I/O to a processor for service or
attention
Priority interrupt bus sends
interrupt signals
Interrupter provides status and ID
info
Have an interrupt handler for each
request line
Can use message passing on data lines
Save lines, but use cycles
Use of time-shared data bus lines
is a virtual-interrupt Reference{ Advance computer architecture ,Kai Hwang} |
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