UNIT – III

INTRODUCTION

Unit-03/Lecture-01

Input Output Organization

·         Modes of data transfer

·         Interrupt driven

·         Direct memory access

·         Interrupt structures

·         I/O Interface

·         Asynchronous data transfer

·         I/O processor

·         8085 I/O structure

·         8085 instruction set and basic programming

·         Data transfer – Serial / parallel

·         synchronous/asynchronous

·         Simplex/half duplex and full duplex

Modes of data transfer

Modes of transfer refer to the various modes by which the data residing in the memory is transferred to CPU or back to memory.

The need to transfer data: The data originates from the input units. The originated data is then transferred to the memory for storage. This binary data received from any external device is in general stored in memory for later processing. So there is need to transfer data . Then for processing the data residing in memory is read by the computer brain i.e. CPU for carrying out various operations and transforming it to make it useful information. The CPU temporarily stores data just for the time being of executing the operation. After that the CPU also need to transfer the information back to the memory.

There are lot of transferring between the CPU and the memory for reading or writing of data or information respectively. There are various modes of transfer of data. Some uses the CPU as in between the transfer and some directly transfers the data to and from the memory unit. Data to and from the peripherals are handled in one of the three possible modes:

1.       Programmed input-output

2.       Interrupt- initiated input output

3.       Direct memory access

 Programmed input-output

Programmed I/O (PIO) refers to data transfers initiated by a CPU under driver software control to access registers or memory on a device.

The CPU issues a command then waits for I/O operations to be complete. As the CPU is faster than the I/O module, the problem with programmed I/O is that the CPU has to wait a long time for the I/O module of concern to be ready for either reception or transmission of data. The CPU, while waiting, must repeatedly check the status of the I/O module, and this process is known as Polling. As a result, the level of the performance of the entire system is severely degraded.

Programmed I/O basically works in these ways:

• CPU requests I/O operation

• I/O module performs operation

• I/O module sets status bits

• CPU checks status bits periodically

• I/O module does not inform CPU directly

• I/O module does not interrupt CPU

• CPU may wait or come back later

 Interrupt

The CPU issues commands to the I/O module then proceeds with its normal work until interrupted by I/O device on completion of its work.

-> Here the program enters a wait loop in which it repeatedly checks the device status. During this process the processor is not performing any useful computation.

->There are many situations where tasks can be performed while waiting for an I/O device to be ready, to allow this the I/O device should alert the processor when it becomes ready. It can be done by sending a hardware signal called an interrupt.

->The routine executed in response to an interrupt request is called Interrupt Service Routine(ISR).

->The processor first completes execution of instruction then it loads the program counter(pc) with the address of 1st instruction of ISR.

For input, the device interrupts the CPU when new data has arrived and is ready to be retrieved by the system processor. The actual actions to perform depend on whether the device uses I/O ports, memory mapping.

For output, the device delivers an interrupt either when it is ready to accept new data or to acknowledge a successful data transfer. Memory-mapped and DMA-capable devices usually generate interrupts to tell the system they are done with the buffer.

Although Interrupt relieves the CPU of having to wait for the devices, but it is still inefficient in data transfer of large amount because the CPU has to transfer the data word by word between I/O module and memory.

Below are the basic operations of Interrupt:

• CPU issues read command

• I/O module gets data from peripheral whilst CPU does other work

• I/O module interrupts CPU

• CPU requests data

• I/O module transfers data

DMA based data transfer

• The transfer of data between a fast storage device such as magnetic disk and memory is often limited by the speed of the CPU.

• Removing the CPU from the path and letting the peripheral device manage the memory buses directly would improve the speed of transfer.

• This transfer technique is called direct memory access (DMA).

• During DMA transfer, the CPU is idle and has no control of the memory buses.

• Two control signals in the CPU that facilitate the DMA transfer.
• Bus request (BR)
• Bus grant (BG)

• The bus request (BR) input is used by the DMA controller to request the CPU to relinquish control of the buses.
• When this input is active, the CPU terminates the execution of the current instruction. The CPU activates the bus grant (BG) output to inform the external DMA that the buses are in the high-impedance state.

• The DMA that originated the bus request can now take control of the buses to conduct memory transfers without processor intervention.

• When the DMA terminates the transfer, it disables the bus request line. The CPU disables the bus grant, takes control of the buses, and returns to its normal operation.

• When the DMA takes control of the bus system, it communicates directly with the memory.

By DMA approach , large blocks of data at high speed can be sent between external device and main memory.

DMA CONTROLLER:-

->It allows the data transfer between I/O device and memory.

->DMA controllers acts a processor but it is controlled by the CPU. To initiate the transfer of a block of words, the processor sends the following data to controller

• Starting address of memory block

• The word count

• Control to specify the mode of transfer such as read or write.

• A control to start the DMA transfer.

->The DMA controller performs the required I/O operation and send a interrupt to the processor upon completition.

Types of DMA Transfer:-

• Cycle stealing

• Brust mode

Cycle Stealing:-

DMA controller ‘steals’ memory cycles from the processor though processor originates most memory access. Allows DMA controller to transfer one data word at a time after

which it must return control of the buses to the CPU.

Brust mode:- 

The DMA controller may be given exclusive access to the main memory to transfer a block of data without interruption.

Conflicts Of DMA:-

->Conflict between processor and DMA

->Two DMA Controller try to access the BUS at same time to access the main memory.

Unit-03/Lecture-02

Interrupt structures

·         Interrupt is signals send by an external device to the processor, to request the processor to perform a particular task or work.

·         Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and the microprocessor.

·         The processor will check the interrupts always at the 2nd T-state of last machine cycle.

·         If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral.

·         The vectored address of particular interrupt is stored in program counter.

·         The processor executes an interrupt service routine (ISR) addressed in program counter.

·         It returned to main program by RET instruction.

Types of Interrupts:

 It supports two types of interrupts.

·         Hardware        

·         Software

 Software interrupts:

·         The software interrupts are program instructions. These instructions are inserted at desired locations in a program.

·         The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts can be calculated as follows.

·         Interrupt number * 8 = vector address

·         For RST 5,5 *  8 = 40 = 28H

·         Vector address for interrupt RST 5 is 0028H

Hardware interrupts:

·         An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor.

·         If the interrupt is accepted then the processor executes an interrupt service routine.

The 8085 has five hardware interrupts

 (1) TRAP             (2) RST 7.5             (3) RST 6.5         (4) RST 5.5       (5) INTR

 TRAP:

·         This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.

·         TRAP bas the highest priority and vectored interrupt.

·         TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged.

·         In sudden power failure, it executes a ISR and send the data from main memory to backup memory.

·         The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).

·         There are two ways to clear TRAP interrupt.

              1.By resetting microprocessor (External signal)

               2.By giving a high TRAP ACKNOWLEDGE (Internal signal)

 RST 7.5:

·         The RST 7.5 interrupt is a maskable interrupt.

·         It has the second highest priority.

·         It is edge sensitive. ie. Input goes to high and no need to maintain high state until it recognized.

·         Maskable interrupt. It is disabled by,

                                 1.DI instruction

                                 2.System or processor reset.

                                 3.After reorganization of interrupt.

·         Enabled by EI instruction.

 RST 6.5 and 5.5:

·         The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it recognized.

·         Maskable interrupt. It is disabled by,

               1.DI, SIM instruction

               2. System or processor reset.

               3. After reorganization of interrupt.

·         Enabled by EI instruction.

·         The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

 INTR:

·         INTR is a maskable interrupt. It is disabled by,

                          1.DI, SIM instruction

                          2. System or processor reset.

                          3. After reorganization of interrupt

·         Enabled by EI instruction.

·         Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of ISR.

·         It has lowest priority.

·         It is a level sensitive interrupts.  ie. Input goes to high and it is necessary to maintain high state until it recognized.

·         The following sequence of events occurs when INTR signal goes high.

1. The 8085 checks the status of INTR signal during execution of each instruction.

 2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt acknowledge signal, if the interrupt is enabled.

 3. In response to the acknowledge signal, external logic places an instruction OPCODE on the data bus. In the case of multibyte instruction, additional interrupt acknowledge machine cycles are generated by the 8085 to transfer the additional bytes into the microprocessor.

4. On receiving the instruction, the 8085 save the address of next instruction on stack and execute received instruction.

Unit-02/Lecture-03

Input Output Interface:    

Fig: Input/Output Interface

Input-output interface provides a method for transferring information between internal storage and external I/O devices. Peripherals connected to a computer need special communication links for interfacing them with the central processing unit. The purpose of the communication link is to resolve the differences that exist between the central computer and each peripheral. The major differences are:

1. Peripherals are electromechanical and electromagnetic devices and their manner of operation is different from the operation of the CPU and memory, which are electronic devices. Therefore, a conversion of signal values may be required.

2. The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, and consequently, a synchronization mechanism may be needed.

3. Data codes and formats in peripherals differ from the word format in the CPU and memory.

4. The operating modes of peripherals are different from each other and each must be controlled so as not to disturb the operation of other peripherals connected to the CPU.

     To resolve these differences, computer systems include special hardware components between the CPU and peripherals to supervise and synchronize all input and output transfers. These  components are called interface units because they interface between the processor bus and the peripheral device.

Need for I/O interface

1. Peripherals are electromechanical devices.But CPU and Memory are electronic devices. Therefore conversion of signal values may be required.

2. Data codes and formats in peripherals differ from the word format in CPU and memory.

3. Data transfer rate of peripherals are slower than CPU, So synchronization may be needed.

4. The operating modes of peripherals are different. So they must be controlled so as not to disturb the operation of other peripherals that are connected to CPU. 
    

There are two types for interfacing I/O devices:

1. Memory mapped I/O device.

2. Standard I/O mapped I/O device or isolated I/O mapping.

Isolated I/O: 
     The isolated I/O configuration separates all I/O interface addresses from the memory addresses. In the isolated I/O configuration, the CPU has distinct input and output instructions. In isolated I/O configuration the memory address and I/O address have its own address space. If the address of interface registers are placed on the  address lines the I/O read or I/O write control lines are enabled. If the memory address is placed on the address lines the memory read and memory write control lines are enabled.

Memory - Mapped I/O: 
     In this configuration same address space is used for both memory and I/O. There are no specific I/O instructions. It allows the computer to used the same instructions for both I/O transfers and  memory transfers. Some instructions are memory reference instructions and others are I/O reference. They are only one set of read/write control signals.

Interface Circuits

An I/O interface consists of the circuitry required to connect an I/O device to a computer bus. On one side of the interface, we have bus signals. On the other side,we have a data path with its associated controls to transfer data between the interface and the I/O device – port. We have two types:

Serial port

Parallel port

A parallel port transfers data in the form of a number of bits (8 or 16) simultaneously to or from the device. A serial port transmits and receives data one bit at a time. Communication with the bus is the same for both formats. The conversion from the parallel to the serial format, and vice versa, takes place inside the interface circuit. In parallel port, the connection between the device and the computer uses a multiple-pin connector and a cable with as many wires. This arrangement is suitable for devices that are physically close to the computer. In serial port, it is much more convenient and cost-effective where longer cables are needed.

Typically, the functions of an I/O interface are:

• Provides a storage buffer for at least one word of data

• Contains status flags that can be accessed by the processor to determine

whether the buffer is full or empty

• Contains address-decoding circuitry to determine when it is being addressed

by the processor

• Generates the appropriate timing signals required by the bus control scheme

• Performs any format conversion that may be necessary to transfer data

between the bus and the I/O device, such as parallel-serial conversion in the

case of a serial port

Parallel Port

The hardware components needed for connecting a keyboard to a processor

Consider the circuit of input interface which encompasses (as shown in below figure):

– Status flag, SIN

– R/~W

– Master-ready

– Address decoder

Unit-02/Lecture-04

Asynchronous data transfer

Fig: Asynchronous data transfer

The internal operations in a digital system are synchronized by means of clock pulses supplied by a common pulse generator. Clock pulses are applied to all registers within a unit and all data transfers among internal registers occur simultaneously during the occurrence of a clock pulse. Two units, such as a CPU and an I/O interface, are designed independently of each other.

 If the registers in the interface share a common clock with the CPU registers, the transfer between the two units is said to be synchronous. In most cases, the internal timing in each unit is independent from the other in that each uses its own private clock for internal registers.

In that case, the two units are said to be asynchronous to each other. This approach is widely used in most computer systems. Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted. One way of achieving this is by means of a strobe pulse supplied by one of the units to indicate to the other unit when the transfer has to occur.

 Another method commonly used is to accompany each data item being transferred with a control signal that indicates the presence of data in the bus. The unit receiving the data item responds with another control signal to acknowledge receipt of the data. This type of agreement between two independent units is referred to as handshaking.

The strobe pulse method and the handshaking method of asynchronous data transfer are not restricted to I/O transfers. In fact, they are used extensively on numerous occasions requiring the transfer of data between two independent units. In the general case we consider the transmitting unit as the source and the receiving unit as the destination.

 For example, the CPU is the source unit during an output or a write transfer and it is the destination unit during an input or a read transfer. It is customary to specify the asynchronous transfer between two independent units by means of a timing diagram that shows the timing relationship that must exist between the control signals and the data in the buses. The sequence of control during an asynchronous transfer depends on whether the transfer is initiated by the source or by the destination unit.

There are two types of asynchronous data transmittion methods:-

1. Strobe control

2. Handshaking.

Strobe Control

This method of asynchronous data transfer uses a single control line to time each transfer. The strobe may be activated by the source or the destination unit.

(i) Source Initiated Data Transfer:

·         The data bus carries the information from source to destination. The strobe is a single line. The signal on this line informs the destination unit when a data word is available in the bus.

·         The strobe signal is given after a brief delay, after placing the data on the data bus. A brief period after the strobe pulse is disabled the source stops sending the data.

Fig: Source - initiated strobe for data transfer

(ii) Destination Initiated Data Transfer:

·         In this case the destination unit activates the strobe pulse informing the source to send data. The source places the data on the data bus. The transmission is stopped briefly after the strobe pulse is removed.

·         The disadvantage of the strobe is that the source unit that initiates the transfer has no way of knowing whether the destination unit has received the data or not. Similarly if the destination initiates the transfer it has no way of knowing whether the source unit has placed data on the bus or not. This difficulty is solved by using hand shaking method of data transfer.

Fig:Destination - initiated strobe for data transfer

A Handshaking Protocol

Fig: A Handshaking Protocol

• Three control lines
• ReadReq: indicate a read request for memory
  Address is put on the data lines at the same time

• DataRdy: indicate the data word is now ready on the data lines
  Data is put on the data lines at the same time

• Ack: acknowledge the ReadReq or the DataRdy of the other party

Unit-02/Lecture-05

I/O processor

·            The concept of I/O processor is an extension of the concept of DMA. The I/O processor can execute specialised I/O program residing in the memory without intervention of the CPU.

·            Thus, CPU only needs to specify a sequence of I/O activity to I/O processor. The I/O processor then executes the necessary I/O instructions which are required for the task; and interrupts the CPU only after the entire sequence of I/O activity as specified by CPU have been completed.

·            An advanced I/O processor can have its own memory, enabling a large set of I/O devices to be controlled without much involvement from the CPU.

·            Thus, an I/O processor has the additional ability to execute I/O instructions which provide it a complete control on I/O operations.

·            Thus, I/O processors are much more powerful than DMA which provides only a limited control of I/O device. For example, if an I/O device is busy then DMA will only interrupt the CPU and will inform the CPU again when the device is free while I/O device and once it has found to be free go a head with I/O and when I/O finishes, communicate it to the CPU. The I/O processor is termed as channel in IMB machines.

·            In computer systems which have IOPs the CPU normally do not execute I/O data transfer instructions.

·             I/O instructions are stored in memory and are executed by IOPs. The IOP can be provided with the direct access to the memory and can control the system bus.

·             An IOP can execute a sequence of data transfer instructions involving different memory regions and different devices without intervention of the CPU.

                                                    Fig: Input/Output Processor

Fig: I/O processor

·         Communicate directly with all I/O devices.

·         Fetch and execute its own instruction.

»        IOP instructions are specifically designed to facilitate I/O transfer

»        DMAC must be set up entirely by the CPU

·               Designed to handle the details of I/O processing.

·               Command

Instruction that are read form memory by an IOP

Distinguish from instructions that are read by the CPU

Commands are prepared by experienced programmers and are stored in memory

                          Command word = IOP program

·               CPU - IOP Communication : Fig. 11-20

·               Memory units acts as a message center : Information

·               each processor leaves information for the other 

·         The IOP attaches to the system I/O bus and one or more input/output adapters (IOAs). The IOP processes instructions from the system and works with the IOAs to control the I/O devices.

·         There are many different kinds of IOPs.

o   Some IOPs can only support one type of I/O device. In this case the IOA is embedded in the IOP so you can not remove the IOA or change it.

o   Some IOPs can support multiple device types, but only one at a time. The type of IOA that is attached determines what device can be used. IOAs on these IOPs can be changed with another IOA to support a different I/O device.

o   Some IOPs can support multiple types of I/O devices at the same time. These are known as MFIOPs or CFIOPs (this depends on the type of IOP). IOAs for the supported types of I/O devices attach to the IOP.

·      There are several important I/O devices in the system. These include the load source disk unit, the alternate IPL device, the console, and the electronic customer support hardware. The system needs to know where to locate these special devices on secondary partitions. When you create a logical partition, you need to identify the IOPs that control these important devices:

o   The IOP that controls the disk unit that will be the load source.

o   The IOP that controls the console.

o   The IOP that controls the alternate IPL device.

o   The IOP that controls the electronic customer support line.

·   IOPs must remain dedicated to a single logical partition. You can not share them. All devices connected to an IOP are bound to the same logical partition. You can not switch one I/O device to another logical partition without switching all devices on the IOP.

·   On a shared bus, you can add and remove IOPs from a logical partition without restarting the system.

Three characteristics are useful in organizing the wide variety of I/O systems.

Ø  Behavior : Input (read once), Output (write only) or storage

Ø  Partner: Either Human or a machine at the end of the I/O device.

Ø  Data rate : The peak rate at which the data can be transferred between the i/o devices and main memeory or processor.

Ex : A key board, i/p device used by a human with data rate about 10 bytes per second.

Fig:A typical collection of I/O devices

Unit-03/Lecture-06

8085 I/O structure

·         The 8085 supported up to 256 input/output (I/O) ports, accessed via dedicated Input/Output instructions—taking port addresses as operands. This I/O mapping scheme was regarded as an advantage, as it freed up the processor's limited address space. The IN and OUT instructions are used to read and write I/O port data.

·         8085 Micro Processor is single board Microprocessor training/ Development Kit configured around the most widely used Microprocessor of todays world. Based on 8085 Microprocessor, it can be used to train engineers to control any industrial process and to develop software for 8080 and 8085 based systems.

·         The 8085 communicates with the outside world through a key board having 28 keys and seven segement hexadecimal displays. The kit also has the capability of interacting with CRT Terminal and IBM PC compatible computer system through the serial interface provided on the board.

·         The 8085 model has an extra on board facility of audio cassette interface.

·         The I/O devices are not given separate addresses other than memory i.e. 0000 to FFFF.(64k).but part of the space is reserved for I/O devices. The advantage is any instruction that references memory can also transfer data between an I/O device and the ,as long as the I/O port is assigned to the memory address space rather than to the I/O address space. The register associated with the I/O port is simply treated as memory location register.

·                     Consider an example in which address bit A₁₅ designates whether instructions reference memory or an I/O device.2f A₁₅= 0, a memory register is addressed; If A₁₅= 1, than a memory mapped I/O device is address .this assignment elevates the first 32kbytess of memory address space to memory and second 32k to memory mapped I/O devices. External logic generates devices select pulses for memory mapped I/O only when  = 0, the appropriate address is on the address low and a  or strobe occurs.

·                     Input and output transfer using memory mapped I/O are not limited to the accumulator. For example, same of 8085 A instructions that can be used for input from memory mapped I/O ports.

          MOV r, m move the connects of input port whose address is available in (H,L) reg pair to any internal register.

          LDA addr load the acc with the content of the input port whose address is available as a second and third byte of the instruction.

·                     Other instructions include, ANA M, ADD M, 1HD add (input from two ports and store the contents is reg pair (L) and (H) ADD M and ANA M provide input data transfer and computation in a single instruction. same instruction that out the data from memory mapped ports are

                        MOV M,r

                        STA addr

                        MVI M, data

                       SHLD addr

·                     LHLD and SHLD carry out 16- bit I/O transfers with single instructions which reduce program executive time considerably. The price paid for this added capability is a reduction in directly addressable main memory and the necessity of decoding a 16- bit rather than an 8-bit address.

·                     When a microprocessor puts out an address and generates a control strobe for a memory read, it has no way of determining whether the device that responds with data is a memory device or an I/O device; nor does it care. If only requires that the devices that respond does so with in the allowable access time or uses the READY line to request a sufficient number of WAIT states. The some of true when a  executives a write to memory.2f supplies an address data, and a write strobe and continues its operations, external logic determines whether memory, I/O or anything at all receives the data transferred.

Unit-03/Lecture-07

Instruction Set of 8085:

An Instruction is a command given to the computer to perform a specified operation on given data. The instruction set of a microprocessor is the collection of the instructions that the microprocessor is designed to execute. The instructions described here are of Intel 8085. These instructions are of Intel Corporation. They cannot be used by other microprocessor manufactures. The programmer can write a program in assembly language using these instructions. These instructions have been classified into the following groups:

1.      Data Transfer Group

2.      Arithmetic Group

3.      Logical Group

4.      Branch Control Group

5.      I/O and Machine Control Group

Data Transfer Group

Instructions, which are used to transfer data from one register to another register, from memory to register or register to memory, come under this group. Examples are: MOV, MVI, LXI, LDA, STA etc. When an instruction of data transfer group is executed, data is transferred from the source to the destination without altering the contents of the source. For example, when MOV A, B is executed the content of the register B is copied into the register A, and the content of register B remains unaltered. Similarly, when LDA 2500 is executed the content of the memory location 2500 is loaded into the accumulator. But the content of the memory location 2500 remains unaltered.

1. MOV r1, r2 (Move Data; Move the content of the one register to another).  [r1] <-- [r2]
2. MOV r, m (Move the content of memory register). r <-- [M]
3. MOV M, r. (Move the content of register to memory). M <-- [r]
4. MVI r, data. (Move immediate data to register). [r] <-- data.
5. MVI M, data. (Move immediate data to memory). M <-- data.
6. LXI rp, data 16. (Load register pair immediate). [rp] <-- data 16 bits, [rh] <-- 8 LSBs of data.
7. LDA addr. (Load Accumulator direct). [A] <-- [addr].
8.  STA addr. (Store accumulator direct). [addr] <-- [A].
9. LHLD addr. (Load H-L pair direct). [L] <-- [addr], [H] <-- [addr+1].
10. SHLD addr. (Store H-L pair direct) [addr] <-- [L], [addr+1] <-- [H].
11. LDAX rp. (LOAD accumulator indirect) [A] <-- [[rp]]
12. STAX rp. (Store accumulator indirect) [[rp]] <-- [A].
13. XCHG. (Exchange the contents of H-L with D-E pair) [H-L] <-->  [D-E].

Arithmetic Group

The instructions of this group perform arithmetic operations such as addition, subtraction; increment or decrement of the content of a register or memory. Examples are: ADD, SUB, INR, DAD etc.

1. ADD r. (Add register to accumulator) [A] <-- [A] + [r].
2. ADD M. (Add memory to accumulator) [A] <-- [A] + [[H-L]].
3. ADC r. (Add register with carry to accumulator). [A] <-- [A] + [r] + [CS].
4. ADC M. (Add memory with carry to accumulator) [A] <-- [A] + [[H-L]] [CS].
5. ADI data (Add immediate data to accumulator) [A] <-- [A] + data.
6. ACI data (Add with carry immediate data to accumulator). [A] <-- [A] + data + [CS].
7. DAD rp. (Add register paid to H-L pair). [H-L] <-- [H-L] + [rp].
8. SUB r. (Subtract register from accumulator). [A] <-- [A] – [r].
9. SUB M. (Subtract memory from accumulator). [A] <-- [A] – [[H-L]].
10. SBB r. (Subtract register from accumulator with borrow). [A] <-- [A] – [r] – [CS].
11. SBB M. (Subtract memory from accumulator with borrow). [A] <-- [A] – [[H-L]] – [CS].
12. SUI data. (Subtract immediate data from accumulator) [A] <-- [A] – data.
13. SBI data. (Subtract immediate data from accumulator with borrow). [A] <-- [A] – data – [CS].
14. INR r (Increment register content) [r] <-- [r] +1.
15. INR M. (Increment memory content) [[H-L]] <-- [[H-L]] + 1.
16. DCR r. (Decrement register content). [r] <-- [r] – 1.
17. DCR M. (Decrement memory content) [[H-L]] <-- [[H-L]] – 1.
18. INX rp. (Increment register pair) [rp] <-- [rp] – 1.
19. DCX rp (Decrement register pair) [rp] <-- [rp] -1.
20. DAA (Decimal adjust accumulator) .

The instruction DAA is used in the program after ADD, ADI, ACI, ADC, etc instructions. After the execution of ADD, ADC, etc instructions the result is in hexadecimal and it is placed in the accumulator. The DAA instruction operates on this result and gives the final result in the decimal system. It uses carry and auxiliary carry for decimal adjustment. 6 is added to 4 LSBs of the content of the accumulator if their value lies in between A and F or the AC flag is set to 1. Similarly, 6 is also added to 4 MSBs of the content of the accumulator if their value lies in between A and F or the CS flag is set to 1. All status flags are affected. When DAA is used data should be in decimal numbers.

Logical Group

The Instructions under this group perform logical operation such as AND, OR, compare, rotate etc. Examples are: ANA, XRA, ORA, CMP, and RAL etc.

1. ANA r. (AND register with accumulator) [A] <-- [A] ^ [r].
2. ANA M. (AND memory with accumulator). [A] <-- [A] ^ [[H-L]].
3. ANI data. (AND immediate data with accumulator) [A] <-- [A] ^ data.
4. ORA r. (OR register with accumulator) [A] <-- [A] v [r].
5. ORA M. (OR memory with accumulator) [A] <-- [A] v [[H-L]]
6. ORI data. (OR immediate data with accumulator) [A] <-- [A] v data.
7. XRA r. (EXCLUSIVE – OR register with accumulator) [A] <-- [A] v   [r]
8. XRA M. (EXCLUSIVE-OR memory with accumulator) [A] <-- [A] v  [[H-L]]
9. XRI data. (EXCLUSIVE-OR immediate data with accumulator) [A] <-- [A]
10. CMA. (Complement the accumulator) [A] <-- [A]
11. CMC. (Complement the carry status) [CS] <-- [CS]
12. STC. (Set carry status) [CS] <-- 1.
13. CMP r. (Compare register with accumulator) [A] – [r]
14. CMP M. (Compare memory with accumulator) [A] – [[H-L]]
15. CPI data. (Compare immediate data with accumulator) [A] – data.

The 2nd byte of the instruction is data, and it is subtracted from the content of the accumulator. The status flags are set according to the result of subtraction. But the result is discarded. The content of the accumulator remains unchanged.

16. RLC (Rotate accumulator left) [An+1] <-- [An], [A0] <-- [A7],[CS] <-- [A7].

The content of the accumulator is rotated left by one bit. The seventh bit of the accumulator is moved to carry bit as well as to the zero bit of the accumulator. Only CS flag is affected.

17. RRC. (Rotate accumulator right) [A7] <-- [A0], [CS] <-- [A0], [An] <-- [An+1].

The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to the seventh bit as well as to carry bit. Only CS flag is affected.

18. RAL. (Rotate accumulator left through carry) [An+1] <-- [An], [CS] <-- [A7], [A0] <-- [CS].
19. RAR. (Rotate accumulator right through carry) [An] <-- [An+1], [CS] <-- [A0], [A7] <-- [CS]

Branch Control Group

This group includes the instructions for conditional and unconditional jump, subroutine call and return, and restart. Examples are: JMP, JC, JZ, CALL, CZ, RST etc.

1. JMP addr (label). (Unconditional jump: jump to the instruction specified by the address). [PC] <-- Label.
2. Conditional Jump addr (label): After the execution of the conditional jump instruction the program jumps to the instruction specified by the address (label) if the specified condition is fulfilled. The program proceeds further in the normal sequence if the specified condition is not fulfilled. If the condition is true and program jumps to the specified label, the execution of a conditional jump takes 3 machine cycles: 10 states. If condition is not true, only 2 machine cycles; 7 states are required for the execution of the instruction.
1. JZ addr (label). (Jump if the result is zero)
2. JNZ addr (label) (Jump if the result is not zero)
3. JC addr (label). (Jump if there is a carry)
4. JNC addr (label). (Jump if there is no carry)
5. JP addr (label). (Jump if the result is plus)
6. JM addr (label). (Jump if the result is minus)
7. JPE addr (label) (Jump if even parity)
8. JPO addr (label) (Jump if odd parity)
3. CALL addr (label) (Unconditional CALL: call the subroutine identified by the operand)

CALL instruction is used to call a subroutine. Before the control is transferred to the subroutine, the address of the next instruction of the main program is saved in the stack. The content of the stack pointer is decremented by two to indicate the new stack top. Then the program jumps to subroutine starting at address specified by the label.

4. RET (Return from subroutine)
5. RST n (Restart) Restart is a one-word CALL instruction. The content of the program counter is saved in the stack. The program jumps to the instruction starting at restart location.

I/O and Machine Control Group

This group includes the instructions for input/output ports, stack and machine control. Examples are: IN, OUT, PUSH, POP, and HLT etc.

1. IN port-address. (Input to accumulator from I/O port) [A] <-- [Port]
2. OUT port-address (Output from accumulator to I/O port) [Port] <-- [A]
3. PUSH rp (Push the content of register pair to stack)
4. PUSH PSW (PUSH Processor Status Word)
5. POP rp (Pop the content of register pair, which was saved, from the stack)
6. POP PSW (Pop Processor Status Word)
7. HLT (Halt)
8. XTHL (Exchange stack-top with H-L)
9. SPHL (Move the contents of H-L pair to stack pointer)
10. EI (Enable Interrupts)
11. DI (Disable Interrupts)
12. SIM (Set Interrupt Masks)
13. RIM (Read Interrupt Masks)
14. NOP (No Operation)

Unit-03/Lecture-08

Data transfer –

A given transmission on a communications channel between two machines can occur in several different ways. The transmission is characterised by:

·         the direction of the exchanges

·         the transmission mode: the number of bits sent simultaneously

·         synchronization between the transmitter and receiver

Serial / parallel

The transmission mode refers to the number of elementary units of information (bits) that can be simultaneously translated by the communications channel.

Parallel connection means simultaneous transmission of N bits. These bits are sent simultaneously over N different channels (a channel being, for example, awire, a cable or any other physical medium). The parallel connection on PC-type computers generally requires 10 wires. 

These channels may be:

·         N physical lines: in which case each bit is sent on a physical line (which is why parallel cables are made up of several wires in a ribbon cable)

·         one physical line divided into several sub-channels by dividing up the bandwidth. In this case, each bit is sent at a different frequency...

Since the conductive wires are close to each other in the ribbon cable, interference can occur (particularly at high speeds) and degrade the signal quality... 

In a serial connection, the data are sent one bit at a time over the transmission channel. However, since most processors process data in parallel, the transmitter needs to transform incoming parallel data into serial data and the receiver needs to do the opposite. 

These operations are performed by a communications controller (normally aUART (Universal Asynchronous Receiver Transmitter) chip). The communications controller works in the following manner:

·         The parallel-serial transformation is performed using a shift register. The shift register, working together with a clock, will shift the register (containing all of the data presented in parallel) by one position to the left, and then transmit the most significant bit (the leftmost one) and so on:

·         The serial-parallel transformation is done in almost the same way using a shift register. The shift register shifts the register by one position to the left each time a bit is received, and then transmits the entire register in parallel when it is full:

Unit-03/Lecture-09

Given the problems that arise with a parallel-type connection, serial connections are normally used. However, since a single wire transports the information, the problem is how to synchronize the transmitter and receiver, in other words, the receiver can not necessarily distinguish the characters (or more generally the bit sequences) because the bits are sent one after the other. There are two types of transmission that address this problem:

·         An asynchronous connection, in which each character is sent at irregular intervals in time (for example a user sending characters entered at the keyboard in real time). So, for example, imagine that a single bit is transmitted during a long period of silence... the receiver will not be able to know if this is 00010000, 10000000 or 00000100...

To remedy this problem, each character is preceded by some information indicating the start of character transmission (the transmission start information is called a START bit) and ends by sending end-of-transmission information (called STOP bit, there may even be several STOP bits).

                                                        In asynchronous transmission, data is coded into a series of pulses, including a start bit and a stop bit. A start bit is sent by the sending modem to inform the receiving modem that a character is to be sent. The character is then sent, followed by a stop bit designating that the transfer of that bit is complete.

Two Asynchronous Data Transfer Methods

Strobe pulse

     - A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to occur.

    -   Employs a single control line to time each transfer.

    -   The strobe may be activated by either the source or the destination unit.

Handshaking

     - A control signal is accompanied with each data being transmitted to indicate the presence of data

     - The receiving unit responds with another control signal to acknowledge receipt of the data.

Source-Initiated Strobe for Data Transfer

HANDSHAKING

Strobe Methods

       Source-Initiated

            The source unit that initiates the transfer has no way of knowing whether the destination unit has actually received data

       Destination-Initiated

            The destination unit that initiates the transfer no way of knowing whether the source has actually placed the data on the bus.

·         In a synchronous connection, the transmitter and receiver are paced by the same clock. The receiver continuously receives (even when no bits are transmitted) the information at the same rate the transmitter send it. This is why the transmitter and receiver are paced at the same speed. In addition, supplementary information is inserted to guarantee that there are no errors during transmission.

                                                      In synchronous data transmission, data is sent via a bit-stream, which sends a group of characters in a single stream In order to do this, modems gather groups of characters into a buffer, where they are prepared to be sent as such a stream. In order for the stream to be sent, synchronous modems must be in perfect synchronization with each other. They accomplish this by sending special characters, called synchronization, or syn, characters. When the clocks of each modem are in synchronization, the data stream is sent.

During synchronous transmission, the bits are sent successively with no separation between each character, so it is necessary to insert synchronization elements; this is called character-level synchronization. 

The main disadvantage of synchronous transmission is recognising the data at the receiver, as there may be differences between the transmitter and receiver clocks. That is why each data transmission must be sustained long enough for the receiver to distinguish it. As a result, the transmission speed can not be very high in a synchronous link.

There are 3 different transmission modes characterised according to the direction of the exchanges:

·         A simplex connection is a connection in which the data flows in only one direction, from the transmitter to the receiver. This type of connection is useful if the data do not need to flow in both directions (for example, from your computer to the printer or from the mouse to your computer...).

·         A half-duplex connection (sometimes called an alternating connection orsemi-duplex) is a connection in which the data flows in one direction or the other, but not both at the same time. With this type of connection, each end of the connection transmits in turn. This type of connection makes it possible to have bidirectional communications using the full capacity of the line.

·         A full-duplex connection is a connection in which the data flow in both directions simultaneously. Each end of the line can thus transmit and receive at the same time, which means that the bandwidth is divided in two for each direction of data transmission if the same transmission medium is used for both directions of transmission.