|
UNIT
4 / LECTURE 1 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
INTRODUCTION A memory unit is a device to which binary information is transferred for storage and from which information is retrieved when needed for processing. When data processing takes place. information from memory is transferred to
selected registers in the processing unit. Intermediate and
final results
obtained in the processing unit are transferred back
to be stored in memory. Binary information received from
an input device is
stored in
memory. and information transferred to an output device is taken
from memory. A memory unit is a collection of cells capable
of storing a large quantity of binary information. There are two types of memories that are
used in digital
systems: random-access memory (RAM) and read-only memory (ROM). RAM stores new information for later use. The process of storing new information into memory is referred
to as a memory write
operation.
The process
of transferring the stored information
out of memory is referred to as a memory read operation. RAM can perform both write and read operations. ROM can perform only the read operation. This means that suitable binary information is already stored inside
memory and can be retrieved or read at any
time. However, that information cannot be altered by writing. ROM is a programmable logic device (PLD).
The binary information
that is stored within such a device
is specified in some fashion and then embedded with in the hard ware in a process is referred to as programming the device. The word "programming" here refers to a hardware procedure which specifies the
bits that are inserted into the hardware configuration of the device. ROM is one example of a PLD. Other such units
are the programmable logic array (PLA). programmable array logic (PAL), and the field -programmable
gate array (FPGA). A PLD is an integrated circuit
with internal logic gates connected through
electronic paths that
behave similarly to fuses. In the original state of the device. all the fuses are intact. Programming the device involves blowing those fuse s along the paths that must be removed in order to obtain the particular
configuration
of the desired logic function. In this chapter, we introduce the configuration
of PLDs
and indicate procedures for their use in
the design of digital systems. We also present CMOS FPGAs, which are configured by downloading a stream of bits into the device to
configure
transmission gates to establish the internal connectivity required
by a specified logic function (combinational or sequential). A
typical PLD may have hundreds to millions of gates
interconnected through hundreds to
thousands of internal paths. In order to show
the internal logic diagram of such a device in a concise
form, it is necessary to employ a special gate symbology
applicable to array logic. Figure
below shows the conventional and array logic symbols
for a multiple-input OR
gate. Instead
of having multiple input lines into
the gate. we draw a single line entering the gate.
The input lines are drawn perpendicular
to this single line and are
connected to the gate through internal fuses. In a similar
fashion, we can
draw the array logic for an AND gate.
This type of graphical representation for the inputs
of gates will be used throughout
the chapter in array logic
diagrams.
Conventional and array logic diagrams for OR gate 2. RANDOM -ACCESS MEMORY A
memory unit is a collection
of storage cells. together
with associated circuits needed to transfer
information into and out of a device. The
architecture of memory is such that information
can be selectively retrieved
from any of its internal locations.
The time it takes
to transfer information to or from
any desired random location is
always the same-hence the name random
access memory, abbreviated
RAM. In
contrast, the time required
to retrieve information that is stored
on magnetic tape depends on
the location of the data. A memory unit stores
binary information in groups of
bits called words. A word in
memory is an entity of bits that move in
and out of storage as a unit.
A memory word is a
group of 1 's and 0's and
may represent a number, an instruction,
one or more alphanumeric
characters or any other binary-coded
information. A group of 8 bits is
called a byte. Most
computer memories
use words
that are multiples of
8 bits in length. Thus,
a l6·bit word contains two bytes, and
a 32-bit word is made up of four bytes. The
capacity of a memory
unit is usually stated as the total
number of bytes
that the unit can
store. Communication
between memory and its environment
is achieved through data input
and output lines,
address selection lines,
and control lines that specify
the direct ion of transfer. A
block diagram of a memory unit is shown
in Fig. below. The n
data input line s provide
the information
Block diagram of a memory unit 2.1 Write and
Read Operations The
two operations
that RAM can
perform are the write
and read operations. As
alluded to
earlier. the
write signal
specifies a transfer-in
operation and the
read signal specifies
a transfer out
operation. On accepting
one of
these control
signals. the internal circuits
inside the
memory provide the
desired
operation. The
steps that must
be taken for the
purpose of
transferring a new
word to be
stored into memory
are as follows: l.
Apply the
binary address
of the desired
word to
the address lines. 2.
Apply the data
bits that
must be stored
in memory to the
data input lines. 3.
Activate the
write input. The
memory unit will
then take the
bits from the
input data
lines and store
them in the word specified
by the
address lines. The
steps that must be
taken for the purpose
of transferring a stored word
out of memory
are as follows: 1.
Apply the binary
address of
the desired word
to the address
lines. 2.
Activate the read input. The
memory unit will
then take
the bits from
the word that
has been selected
by the address
and apply them
to the output data lines.
The contents of
the selected word
do not change
after the read
operation.
i.e.. the
word operation is
nondestructive. Commercial
memory components available
in integrated-circuit chips
sometimes provide the
two control inputs for
reading and writing
in a somewhat different
configuration. Instead
of having separate read
and write inputs to
control the two
operations, most integrated
circuits provide two
other control
inputs: One
input selects
the unit and
the other
determines the
operation. The
memory operations that result
from these control
inputs are specified in Table below. The
memory enable
(sometimes called
the chip
select) is
used to
enable
the particular
memory chip in a
multichip implementation of
a large memory.
When the
memory enable is
inactive. the
memory chip
is not selected
and no operation
is performed. When the
memory enable input is
active, the
read/write input determines the
operation to be
performed.
UNIT 4 / LECTURE 2
Types of
Memories [ june 2014(2)] The
mode of
access of a memory
system
is determined
by the
type of components used.
In a random-access
memory, the
word locations
may be thought
of as being
separated in space, each
word occupying
one particular
location.
In a sequential-access
memory,
the information stored
in some
medium
is not
immediately accessible,
but is available
only at
certain intervals of
time.
A magnetic
disk or tape
unit is
of this
type.
Each memory
location passes me
read and write
heads in
turn, but
information
is read
out only
when the
requested word
has been reached. In
a random-access
memory, the
access time
is always the
same regard less of
the particular
location of the
word. In
a sequential-access
memory, the
time it takes
to access
a word depends
on the position
of the word with
respect to the position
of the read head :
therefore, the access
time is variable. Integrated
circuit RAM units
are available in two operating
modes: static
and dynamic.
Static RAM
(SRAM) consists
essentially of internal
latches that
store the binary information.
The stored information
remains valid
as long as power
is applied
to the
unit. Dynamic RAM
(DRAM)
stores
the binary information
in the form of electric
charges o
n capacitors
provided inside the chip
by MOS transistors.
The stored charge
on the capacitors
tends to discharge
with time,
and the capacitors
must
be periodically recharged
by refreshing
the dynamic memory.
Refreshing is
do ne by
cycling through the
words every
few milliseconds
to restore
the decaying charge.
DRAM offers reduced
power consumption
and larger
storage
capacity
in a single
memory chip.
SRAM is easier
to use and
has shorter
read and
write cycles.
Memory
units that
lose stored
information when power
is turned
off are said to be volatile.
CMOS integrated circuit
RAMs, both
static and
dynamic, are
of this category,
since the binary
cells
need external
power to maintain
the stored information. In
contrast, a nonvolatile
memory, such
as magnetic
disk, retains
its stored information after the
removal of power,
This type of memory is able
to retain information
because the data
stored on
magnetic components are
represented by the
direction of
magnetization, which
is retained after
power is
turned off
ROM is
another nonvolatile memory,
A nonvolatile memory enables
digital computers
to store programs
that will be needed again
after the computer
is turned on.
Programs and
data that
cannot be altered
are stored in ROM.
while other
large programs
are maintained on
magnetic dish. The latter
programs are transferred into
the computer
RAM as
needed. Before
the power is
turned off,
the binary
information from
the computer RAM
is transferred to the
disk so that
the information
will be retained. Internal
Construction [june 2014(2)] The
internal construction
of a RAM of
m words and
n bits
per word consists
of m× n binary
storage cells
and associated
decoding circuits
for selecting
individual
words. The
binary storage
cell is
the basic
building block
of a memory
unit. The equivalent
logic of a
binary cell
that stores
one bit of
information
is shown
in Fig. below.
The storage
part of the cell
is modeled
by an SR latch
with associated
gate s to
form a D
latch.
Actually, the
cell is an
electronic circuit
with four to six
transistors. Nevertheless.
it is possible and convenient
to model it in
term s of logic
symbols. A
binary storage
cell must be
very small
in order
to be able to pack as
many cells as
possible in the small
area available
in the
integrated circuit
chip. The binary cell
stores one bit
in its internal latch.
The select
input enables
the cell for
reading or writing,
and the
read/write input determines
the operation
of the cell
when it is
selected. A 1
in the read/write
input provides
the read operation
by fanning a
path from the
latch to
the output terminal. A 0
in the read/write input
UNIT
4 / LECTURE 3
Memory cell
Diagram
of a 4×4 RAM The
logical construction of
a small RAM is shown in
Fig. below.
This RAM consists
of four words
of four bits each and
bas a total of
16 binary cells. The
small blocks labeled BC represent
the binary cell with its
three inputs and
one output.
as specified in Fig.
b above. A memory
with four words
needs two address
lines. The
two address inputs
go through a 2×4 decoder to
select one of the
four
words. The
decoder is enabled
with the memory-enable
input. When
the memory enable
is 0, all
outputs
of the decoder are 0 and
none of the memory
words are selected.
With the memory select
at 1, one
of the
four word four is selected, dictated
by the value in
the two address
lines. Once
a word has been selected.
the read/write
input determines
the operation. During,
the read operation.
the four bits of
the selected
word go through OR gates
to the
output terminals. During
the write
operation. the data
available in the input lines arc transferred
into the
four binary
cells of the
selected word.
The binary cells
that are not
selected are disabled,
and their previous
binary values
remain unchanged. When
the memory select
input that goes into
the decoder is equal to O. none
of the words are
selected and the contents
of all cells
remain unchanged
regardless of the value of
the read/write
input. Commercial
RAMs may have
a capacity of
thousands of words,
and each word
may range from 1to 64 bits.
The logical
construction of a
large-capacity
memory would
be a direct extension
of the configuration shown here .
A memory with 2k
words of n bits
per word
requires k address lines
that go into
a k×2k; decoder.
Each one of
the decoder outputs selects one
word of n bits for
reading or writing. READ-ONLY MEMORY A
ROM is essentially a memory
device in which
permanent binary information
is stored.
The binary
information
must be specified
by the designer
and is then
embedded in the
unit to form
the required interconnection
pattern. Once
the pattern is
established, it stays within
the unit even
when power
is turned
off and on again. A
block diagram
of a ROM
consisting of k inputs
and n outputs is shown
in Fig.
below. The inputs
provide the
address for memory,
and the outputs give
the data bits
of the stored
word that is selected by the
address. The number
of words in a
ROM is determined
from the fact that
k address input lines
are needed to
specify 2k words.
Note that
ROM does not have
data inputs,
because it does
not have
a write operation. Integrated
circuit ROM chips have
one or more enable inputs
and sometimes
come with three
-state outputs to facilitate the
construction of large
arrays of ROM.
ROM block
diagram Consider,
for example. a 32
X 8 ROM. The
unit consists of
32 word s of 8 bits
each. There
are five input
lines that form
the binary number
s from 0 through 31
for the address.
Figure below shows
the internal
logic construction of this
ROM. The
five inputs
are decoded
into 32 distinct
outputs
by means of a 5 X 32 decoder.
Each output of
the decoder represents
a memory address. The
32 outputs
of the decoder are
connected to each
of the eight OR gates.
The diagram
shows the array
logic convention used
in complex circuits.
Each OR gate must
be considered
as having 32
inputs. Each
output of
the decoder is connected
to one of the inputs of each OR gate.
Since each OR gate has 32 input
connections and there
are 8 OR
gates, the
ROM contains
32 x 8 =
256 internal connections.
In general, a
2k×n ROM will
have an internal k
×2k decoder
and n
OR gates. Each
OR gate has
2k inputs,
which are connected
to each of the
outputs
of the
decoder. The
256 intersections
in Fig.
below are programmable. A
programmable connection between
two lines is logically
equivalent to a switch
that can be altered to
be either closed (meaning
that the two
lines are connected)
or open (meaning
that the two lines
are disconnected).
The programmable
intersection
between two lines
is sometimes
called a crosspoint.
Various physical
devices are
used to implement
crosspoint switches.
One of
the simplest
technologies employs
a fuse that
normally connects
the two points, but is opened or "blown"
by the application
of a high-voltage
pulse into the
fuse.
Internal
logic of a 32 x 8 ROM The
internal binary storage
of a ROM is specified by a truth tab
le that
shows the
word content in each
address. For
example, the content of
a 32 X 8 ROM may
be specified with
a truth table
similar to the
one shown
in Table below. The
truth table shows the five inputs
under which
are listed all 32
addresses. Each
address stores
a word of
8 bits.
which is
listed in
the outputs
columns.
The table
shows
only the
first four and the last four
words in the ROM.
The complete
table must
include the list
of all 32 words.
ROM Truth Table (Partial) The
hardware
procedure that
programs the
ROM blows
fuse links
in accordance with
a given truth
table. For example,
programming the ROM
according to
the truth table given
by table
above results
in the configuration
shown in Fig above.
Every 0 listed
in the
truth table specifies
the absence
of a connection,
and every
1 listed
specifies a path
that is obtained
by a connection.
For example, the
table specifies the
eight-bit word 10110010
for permanent
storage at
address
3. The four O's
in the word are
programmed
by blowing the
fuse links between
output 3 of the
decoder and
the inputs
of the OR gates
associated with
outputs
A6, A3, A2and A1.
The four l 's
in the word are
marked with a X
to denote a
temporary connection,
in place
of a dot
used for a permanent
connection in
logic diagrams.
When the
input of the ROM
is 00011,
all the outputs of the
decoder are 0 except
for output
3, which
is at logic
1. The signal
equivalent to logic 1 at
decoder output 3 propagates
through the
connections to the OR
gate outputs
of A7, A5, A4 and
A1. The
other four outputs
remain at 0. The
result is that
the stored word 10110010
applied to the eight data
outputs. 3.1
Types of ROMs [june 2014(7)] The
required paths
in a ROM
may be programmed in
four different ways.
The first is
called mask
programming and is
done by the semiconductor
company during
the last
fabrication
process of
the unit.
The procedure
for fabricating
a ROM requires
that the customer
fill out
the truth table
he or
she wishes
the ROM to
satisfy.
The truth table
may be submitted
in a special form
provided
by the
manufacturer or in
a specified form
at on a
computer
output
medium. The
manufacturer
makes the
corresponding
mask for
the path
s to produce
the 1's
and 0's according
to the customer's
truth table.
This procedure
is costly
because
the vendor
charges the customer
a special
fee for
custom masking
the particular
ROM. For
this reason,
mask programming
is economical
only if
a large
quantity of
the same ROM
configuration is
to be ordered. For
small quantities,
it is more
economical
to use a second
type
of ROM called
programmable read-only
memory, or PROM.
When ordered, PROM
units contain
all the
fuses intact,
giving all
l s in the
bits of the
stored
words.
The fuses
in the PROM
are blown
by the
application of
a high-voltage pulse
to the device
through a special
pin. A
blown fuse defines
a binary
0 state and
an intact fuse
gives a binary
I state.
This procedure
allows the user to program
the PROM in
the laboratory to
achieve
the desired
relationship
between input addresses
and stored words. Special instruments
called PROM programmers are available
commercially to facilitate
the procedure.
In any case, all
procedures for programming ROMs are hardware
procedure s,
even though the word programming
is used. The
hardware procedure
for programming ROMs
or PROMs
is irreversible,
and once
programmed, the fixed
pattern is permanent
and cannot
be altered. Once
a bit pattern
has been established,
the unit must
be discarded
if the bit
pattern is
to be changed.
A third type of
ROM is
the erasable
PROM, or EPROM,
which can
be restructured to
the initial
state even though it
has been
programmed previously.
When the
EPROM is
placed under a special
ultraviolet
light for a
given length of time,
the shortwave
radiation discharges
the internal floating
gates that
serve as the
programmed connections.
After erasure,
the EPROM returns
to its
initial state
and can be reprogrammed to
a new set of values. The
fourth type of ROM is
the electrically erasable
PROM (EEPROM or
E2PROM ). This
device is like
the EPROM,
except that the previously
programmed connections can
be erased with
an electrical signal
instead
of ultraviolet
light. The
advantage is
that the device
can be erased
without removing
it from its
socket. Flash
memory devices are similar
to EEPROMs,
but have additional built-in
circuitry to selectively
program and erase the device in-circuit,
without
the need for
a special programmer. They have
widespread application
in modern technology
in cell phones, digital
cameras set top
boxes, digital TV,
telecommunications, non volatile data
storage and
microcontrollers. Their
low consumption of power makes them
an attractive
storage medium
for laptop and notebook computers.
Flash memories
incorporate additional
circuitry, too
allowing simultaneous
erasing of
blocks of memory,
for example, of
size 16 Kbytes
to 64 Kbytes.
Like EEPROMs, flash
memories
are subject to fatigue,
typically
having
about 105
block erase
cycles. UNIT 4 / LECTURE 4
Q1.
Consider that the following Boolean functions are to be developed using ROM. F1
(A, B, C) = ( 0,1,2,5,7) and F2
(A, B, C) = (1,4,6). When
a combinational circuit is developed by means of a ROM, the functions must be
expressed in the sum of minterms or by a truth table. The truth table of the
above functions is shown in Figure 6.6. Since there are three input
variables, a ROM containing a 3-to-8 line decoder is needed. In addition,
since there are two output functions, the OR array must contain at least two
OR gates. That means, a 23 × 2 ROM or 8 × 2 ROM is to be
employed to realize the above functions. The logic diagram of the ROM after blowing
off the appropriate fuses is illustrated in Figure 6.7. Obviously, this is
too simple a combinational circuit to be implemented with a ROM. This example
is merely for illustration purpose only. From the practical point of view,
the real advantage of a ROM is in implementation of complex combinational
networks having a large number of inputs and outputs. Some
ROM units are available with INVERTERs after each of the OR gates and they
are specified as having initially all 0s at their outputs. The programming
procedure in such ROMs require to blow off the link paths of the minterms (or
addresses) that specify an output of 1 in the truth table. The outputs of the
OR gates will then generate the complements of the functions, but the
INVERTERs placed after OR gates complement the functions once more to provide
the desired outputs
Figure : 1 Q 2. Find the squares of 3-bit numbers. Solution.
This example has already been discussed and implemented with the classical
method in Chapter 5. There are three input variables and six output
functions. To implement with ROM, a 23 × 6 ROM or 8 × 6 ROM
is required. The truth table is again shown below for convenience. Figure 2.1
shows the inputs and outputs with ROM and the internal fusible junctions are
shown in Figure 2.2 after programming.
figure 2.1
figure 2.2 UNIT
4 /LECTURE 5
PROGRAMMABLE
LOGIC ARRAY [june 2014(7)] The
PLA is similar
in concept
to the
PROM, except
that the
PLA does not
provide full decoding
of the variables and
does not
generate all
the minterms.
The decoder
is replaced
by an array
of AND gates
that can
be programmed to generate
any product term
of the input
variables. The
product
terms are then
connected to OR
gates to provide
the sum of
products for
the required
Boolean functions.
The
internal logic
of a PLA with
three inputs
and two outputs
is shown in
Fig. below. Such a
circuit is
too small
to be useful
commercially, but
is presented here
to demonstrate
the typical
logic configuration
of a PLA.
The diagram
uses the
array logic graphic
symbols for
complex circuits.
Each input
goes through a buffer-inverter
combination, shown
in the diagram
with a composite
graphic symbol,
that has both
the true
and complement
outputs.
Each input
and its
complement is connected
to the
inputs of
each AND
gate, as indicated
by the intersections
between the vertical
and horizontal
lines. The outputs
of the AND
gates are connected to
the inputs
of each OR
gate. The
output of
the OR gate
goes to an
XOR gate,
where
the other
input can
be programmed to
receive a signal equal
to either logic
1 or logic
0. The output
is inverted when
the XOR input
is connected
to 1 (since
x xor 1 =
x'). The
output
does not
change
when the XOR input
is connected
to 0 (since
x xor 0 =
x) . The particular
Boolean functions
implemented in
the PLA
of Fig.
above are F1
= AB’ + AC + A’BC’ F2
= (AC + BC)’ Combinational Circuit Implementation with PLA When implementing combinational circuit using
PLA, we must reduce the numberof product terms.Number of literals in each
product term is not importent because all variables and their complements are
available . In order to reduce the
number of product terms , we have to simplify the functions and their complements in order to fine the combination
that results in the minimum number of product terms. The size of the PLA is determined bu the no. of
inputs,numper of product terms and no. of outputs. Q1.
Implement the following two Boolean functions using a PLA.
The minimum number of product terms is (4) and is
obtained if F1 in complement form and F2in true form.
UNIT 4 /
LECTURE 6
PROGRAMMABLE
ARRAY LOGIC The
PAL is
a programmable
logic
device
with a fixed
OR array and
a programmable
AND array.
Because
only
the AND
gates
are programmable,
the PAL
is easier
to program
than. but
is not as
flexible
as, the
PLA. Figure
below shows,
the logic
configuration
of a typical
PAL with four
inputs
and four
outputs.
Each input
has a buffer-
inverter gale,
and each
output is generated
by a fixed
OR gate.
There are four
sections
in the
unit, each
composed
of an AND-OR array that
is three
wide. the
term used to
indicate
that there
arc three
programmable
AND gates
in each
section and
one fixed
OR gate.
Each AND
gate has
10 programmable input
connections,
shown
in the diagram
by 10 vertical
lines intersecting
each horizontal
line. The
horizontal line
symbolizes
the multiple-input
configuration
of the AND gate.
One of the
outputs is
connected to a buffer-inverter
gate and then fed back into
two inputs
of the AND
gates. Commercial
PALdevices contain
more gates than
the one shown
in Fig.
below. A typical
PAL integrated
circuit may have
eight inputs,
eight outputs,
and eight
sections,
each
consisting
of an
eight-wide AND
-OR array.
The output
terminals are sometimes
driven
by three-state
buffers
or inverters. In
designing
with a PAL,
the Boolean
functions
must be simplified
to fit into
each
section.
Unlike
the situation
with a PLA,
a product
term cannot
be shared
among two
or more OR
gates.
Therefore,
each function
can be simplified
by itself,
without regard
to common
product
terms. The
number of
product terms
in each section
is fixed,
and if the
number of
terms in
the function
is too large.
it may be necessary
to use
two sections
to implement one
Boolean
function. As
an example
of using a
PAL in the design
of a combinational
circuit, consider me
following Boolean
functions,
given in sum-of-minterms
form: w (A, B, C, D) = ∑(2, 12, 13) x (A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 12, 14, 15) y (A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) z (A, B, C, D) = ∑(1, 2, 8, 12, 13) Simplifying
the four
functions
to a minimum
number
of terms
results
in the
following Boolean
functions: w = ABC’ + A’B’CD’ x = A + BCD y = A’B + CD + B’D’ z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D Note
that
the function
for c has
four product
terms. The
logical
sum of
two of
these
terms
is equal
to w.
By using
w, it
is possible
to reduce
the number of
terms for z
from four
to three. The
PAL programming
table is
similar to the: one
used for
the PLA,
except that
only the inputs
of the
AND gates
need to
he programmed.
Table below
lists the
PAL programming
table for the four
Boolean
functions. The table
is divided
into four sections
with three product
terms in each,
to conform with the PAL
of Fig. below.
The first
two sections
need only two product terms
to PAL with four Inputs, four
outputs, and a three- wide AND-OR structure UNIT 4 / LECTURE 7
Implement
the Boolean function.
The last section, for
output z, needs
four product
terms. Using
the output from w,
we can reduce the function to
three terms. The
PAL programming
table is
similar to the: one
used for
the PLA.
except that
only the inputs
of the
AND gates
need to
he programmed.
Table below
lists the
PAL programming
table for the four
Boolean
functions. The table
is divided
into four sections
with three product
terms in each,
to conform with the PAL
of Fig. below.
The first
two sections
need only two product terms
to implement
the Boolean function.
The last section, for
output z, needs
four product
terms. Using
the output from w,
we can reduce the function 10
three terms. The
fuse map for the PAL
as specified in the
programming table
is shown in Fig.
below. For
each 1 or
0 in the table, we mark the corresponding
intersection in the diagram with
the symbol for an
intact fuse. For
each dash,
we mark the diagram with blown
fuses in both the true and complement
inputs. If the AND gate
is not used,
we leave
all its input fuses intact.
Since the corresponding
input receive s
both the true
value and the complement
of each input
variable, we
have AA’ = 0
and the output of
the AD gale is always
0. As
with all PLDs.
the design with
PALs is
facilitated by
using
computer-aided
design techniques.
The blowing of internal fuses
is a hardware procedure
done with the help of special
electronic instruments.
Fuse
map for PAL as specified in Table Above UNIT
4 / LECTURE 8
Random-access memory(RAM) Random-access memory (RAM
/rćm/) is a form of computer data storage. A random-access memory device allows data items to be read and written in approximately the
same amount of time regardless of the order in which data items are accessed.[1] In contrast, with
other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the older drum memory, the time
required to read and write data items varies significantly depending on their
physical locations on the recording medium, due to mechanical limitations such
as media rotation speeds and arm movement delays. Types of
RAM [dec 2014(3)]
The
two main forms of modern RAM are static
RAM
(SRAM) and dynamic
RAM
(DRAM). In SRAM, a bit of data is
stored using the state of a six transistor memory
cell.
This form of RAM is more expensive to produce, but is generally faster and
requires less power than DRAM and, in modern computers, is often used as
cache memory for the CPU.
DRAM stores a bit of data using a transistor and capacitor pair, which
together comprise a DRAM memory
cell.
The capacitor holds a high or low charge (1 or 0, respectively), and the
transistor acts as a switch that lets the control circuitry on the chip read
the capacitor's state of charge or change it. As this form of memory is less
expensive to produce than static RAM, it is the predominant form of computer
memory used in modern computers. Both
static and dynamic RAM are considered volatile, as their state is lost
or reset when power is removed from the system. By contrast, read-only memory
(ROM) stores data by permanently enabling or disabling selected transistors,
such that the memory cannot be altered. Writeable variants of ROM (such as EEPROM and
flash
memory)
share properties of both ROM and RAM, enabling data to persist
without power and to be updated without requiring special equipment. These
persistent forms of semiconductor ROM include USB
flash drives, memory cards for cameras and portable devices, etc. ECC memory
(which can be either SRAM or DRAM) includes special circuitry to detect
and/or correct random faults (memory errors) in the stored data, using parity bits or error
correction code. In
general, the term RAM refers solely to solid-state memory devices
(either DRAM or SRAM), and more specifically the main memory in most
computers. In optical storage, the term DVD-RAM is
somewhat of a misnomer since, unlike CD-RW or DVD-RW it
does not need to be erased before reuse. Nevertheless a DVD-RAM behaves much
like a hard disc drive if somewhat slower. Synchronous
dynamic random-accessmemory (SDRAM)
Synchronous dynamic random access memory (SDRAM) is dynamic
random access memory (DRAM) that is synchronized with the system bus.
Classic DRAM has an asynchronous interface, which means that it responds as
quickly as possible to changes in control inputs. SDRAM has a synchronous
interface, meaning that it waits for a clock signal
before responding to control inputs and is therefore synchronized with the
computer's system bus. The clock is used to drive an internal finite
state machine that pipelines incoming commands. The data storage area
is divided into several banks, allowing the chip to work on several
memory access commands at a time, interleaved among the separate banks. This
allows higher data access rates than an asynchronous DRAM. Pipelining
means that the chip can accept a new command before it has finished
processing the previous one. In a pipelined write, the write command can be
immediately followed by another command, without waiting for the data to be
written to the memory array. In a pipelined read, the requested data appears
after a fixed number of clock cycles after the read command (latency), clock
cycles during which additional commands can be sent. (This delay is called
the latency and
is an important performance parameter to consider when purchasing SDRAM for a
computer.) SDRAM
construction and operation
For
example, a 512 MB
SDRAM DIMM (which contains 512 MiB
(mebibytes)
= 512 × 220 bytes = 536,870,912 bytes
exactly), might be made of eight or nine SDRAM chips, each containing
512 Mbit
of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit
width. A typical 512 Mbit SDRAM chip internally contains 4 independent
16 MB (MiB)
memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. A bank
is either idle, active, or changing from one to the other. The
active command activates an idle bank. It presents a two-bit bank
address (BA0–BA1) and a 13-bit row address (A0–A12), and causes a read of
that row into the bank's array of all 16,384 column sense amplifiers. This is
also known as "opening" the row. This operation has the side effect
of refreshing the
dynamic (capacitive) memory storage cells of that row. Once
the row has been activated or "opened", read and write
commands are possible to that row. Activation requires a minimum amount of
time, called the row-to-column delay, or tRCD before reads or
writes to it may occur. This time, rounded up to the next multiple of the
clock period, specifies the minimum number of wait cycles between an active
command, and a read or write command. During these wait cycles,
additional commands may be sent to other banks; because each bank operates completely
independently. Both
read and write commands require a column address. Because each
chip accesses eight bits of data at a time, there are 2048 possible column
addresses thus requiring only 11 address lines (A0–A9, A11). When
a read command is issued, the SDRAM will produce the corresponding
output data on the DQ lines in time for the rising edge of the clock a few
clock cycles later, depending on the configured CAS latency. Subsequent words
of the burst will be produced in time for subsequent rising clock edges. A
write command is accompanied by the data to be written driven on to
the DQ lines during the same rising clock edge. It is the duty of the memory
controller to ensure that the SDRAM is not driving read data on to the DQ
lines at the same time that it needs to drive write data on to those lines.
This can be done by waiting until a read burst has finished, by terminating a
read burst, or by using the DQM control line. When
the memory controller needs to access a different row, it must first return
that bank's sense amplifiers to an idle state, ready to sense the next row.
This is known as a "precharge" operation, or "closing"
the row. A precharge may be commanded explicitly, or it may be performed
automatically at the conclusion of a read or write operation. Again, there is
a minimum time, the row precharge delay, tRP, which must elapse
before that bank is fully idle and it may receive another activate command. Although
refreshing a row is an automatic side effect of activating it, there is a minimum
time for this to happen, which requires a minimum row access time tRAS
delay between an active command opening a row, and the corresponding
precharge command closing it. This limit is usually dwarfed by desired read
and write commands to the row, so its value has little effect on typical
performance.
Dynamic random-access memory(DRAM)
[dec 2014(7)] Dynamic random-access memory (DRAM) is a type of random-access
memory
that stores each bit of
data in a separate capacitor
within an integrated
circuit.
The capacitor can be either charged or discharged; these two states are taken
to represent the two values of a bit, conventionally called 0 and 1. Since
even "nonconducting" transistors always leak a small amount, the
capacitors will slowly discharge, and the information eventually fades unless
the capacitor charge is refreshed
periodically. Because of this refresh requirement, it is a dynamic
memory as opposed to static
random access memory (SRAM) and other static types of memory. The
main memory (the "RAM") in personal computers is dynamic RAM
(DRAM). It is the RAM in desktops, laptops and
workstation
computers as well as some of the RAM of video game
consoles. The
advantage of DRAM is its structural simplicity: only one transistor and
a capacitor are required per bit, compared to four or six transistors in
SRAM. This allows DRAM to reach very high densities.
Unlike flash
memory,
DRAM is volatile
memory
(vs. non-volatile
memory),
since it loses its data quickly when power is removed. The transistors and
capacitors used are extremely small; billions can fit on a single memory chip. Due
to the nature of its memory
cells,
DRAM consumes relatively large amounts of power, with different ways for
managing the power consumption. Operation principle
DRAM
is usually arranged in a rectangular array of charge storage cells consisting
of one capacitor and transistor per data bit. The figure to the right shows a
simple example with a four-by-four cell matrix. Some DRAM matrices are many
thousands of cells in height and width. The
long horizontal lines connecting each row are known as word-lines. Each
column of cells is composed of two bit-lines, each connected to every other
storage cell in the column (the illustration to the right does not include
this important detail). They are generally known as the "+" and
"−" bit lines. Operations
to read a data bit from a DRAM storage cell
5.
The sense
amplifiers are now connected to the bit-lines pairs. Positive feedback then
occurs from the cross-connected inverters, thereby amplifying the small
voltage difference between the odd and even row bit-lines of a particular
column until one bit line is fully at the lowest voltage and the other is at
the maximum high voltage. Once this has happened, the row is "open"
(the desired cell data is available).
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
